Dwarkesh Podcast · Thursday, October 22, 2026
Intel discussed its manufacturing strategy for the upcoming 14A process node, explaining that the use of backside power alleviates front-side pitch constraints and makes high-NA EUV lithography tools economically and practically viable. They contrasted this with competitors like TSMC, which rely on double-patterning EUV due to different architectural choices.
“We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side. And that allows you to print that directly with Hainé.”