No Priors · Friday, October 2, 2026
Walter Goodwin believes the timeline for fully automating chip design from intent to GDS2 file is shorter than industry predictions. He highlights that while AI can automate many design tasks, computational bottlenecks in areas like layout and simulation will persist, requiring continued innovation.
“I was talking to one of the top three semi-CEOs, and he wouldn't let me put this prediction, you know, actually on air. But I asked him, like, how soon until we can have essentially, like, intent from chief architect into a fully usable GDS2 file? And he's like, 10 years. Yeah. It's not going to happen, like, now. What is your view on that?”
“So I think we see this in AI for guiding AI model development today, so the RSI work. Yes, we can now have extreme intelligence that is guiding our experiments, but now we're just experiment bottlenecked. We're compute time bottlenecked. And so I think with chip design, it's a little bit like this.”
“The other part there, and I think this is true of, you know, RSI for AI experiments as well, the thinking that then drives that experiment gets higher and higher. And as that experiment, therefore becomes the bottleneck, I think we do more thinking.”